VLSI 2024, semiconductor giants showcase the latest technology

Based on the number of papers submitted and accepted from various regions this year, Mainland China has the highest number of submitted papers, with 237 articles.

The International Conference on Very Large Scale Integration (VLSI Symposium) 2024 will be held in Hawaii, USA, from June 16th to 20th, 2024.

Looking at the annual trend of the number of papers submitted from various regions, there has been an increase in the number of papers submitted from North America, Europe, South Korea, Taiwan, Mainland China, Singapore, and other areas compared to the previous year. The growth in Mainland China is particularly noticeable. In terms of the number of papers accepted from various regions, South Korea and North America have jointly taken the lead. The number of applications from Mainland China is also on the rise.

From the number of papers submitted and accepted from various regions this year, Mainland China has the highest number of submitted papers, with 237 articles. It is followed by South Korea (187 articles) and North America (167 articles). In terms of the number of papers accepted, North America and South Korea are tied for first place with 54 papers each. Third place is Mainland China, with 37 projects accepted. Europe is closely behind China, with 36 papers.

How does the "Intel 3" process improve performance by 18%?

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In the "Device/Process Technology Field," 5 projects come from "The Latest and Next Generation CMOS Logic Device/Process Technology," 4 projects come from "Next Generation Storage Technology," and 1 project comes from "All-oxide Material" transistor technology. A total of 11 papers were selected as notable papers, one of which is from "Angstrom Generation PPA Performance Evaluation Considering Thermal Effects."The article titled "The Latest Next-Generation Devices/Process Technologies of CMOS Logic" includes a technical overview of Intel's cutting-edge mass production process "Intel 3" and Intel's 2.5D packaging technology "Foveros" (numbered T1-1). The development results of creating high-density MIM capacitors (numbered T9-1) have been selected as a featured paper.

Intel has disclosed detailed information about its latest "Intel 3" process node. It has begun mass production in the fourth quarter of 2023 and is used in the previously released "Xeon 6".

Intel 3 is developed based on "Intel 4" and is currently adopted in the Core Ultra for personal use, and is now in mass production. Compared with the previous Intel 4, it can enhance the performance of the processor core by up to 18% and the density by up to 10% at the same power. This performance improvement is equivalent to the evolution of a generation.

This is achieved by optimizing almost every aspect of the process from the transistor to the metal stack. In addition to the 240nm high-performance, the library also has a 210nm high-density.

Specifically, the width and height have been improved to form straighter fins, which enables better channel control and lower power operation. We have also introduced a bipolar work function, which improves the low power performance characteristics by 15%.

Other improvements include improved contact, gate, and gate via designs to reduce switching speed, increase power consumption, overlapping capacitance that may lead to signal delay, and reduce contact line resistance.

In addition to Intel 3, the Intel 3 process will also introduce three variants in stages to reduce risk.Intel 3-T: Provides Through-Silicon Vias (TSVs) for 3D stacking applications, such as image processing/high-performance computing/AI that require the integration of multiple computing and memory components into a single package.

Intel 3-E: Adds I/O sets for external interfaces, analog, and mixed-signal functions. Used for chipsets and storage.

Intel 3-PT: Built on Intel 3-E, it makes it easier for designers to work and supports performance enhancements, fine-pitch 9µm TSVs, and hybrid bonding options for high-density 3D stacking. It is set to be the mainstay for both internal and external use in the coming years.

To regain the leading position in semiconductor manufacturing technology, Intel has formulated the "5N4Y" roadmap, which aims to achieve five nodes within four years, with the implementation of Intel 3 being part of this roadmap. The company has stated that it will launch the Intel 20A and Intel 18A processes next year, featuring the latest technologies such as RibbonFET and Angstrom.

Additionally, Samsung Electronics has developed a 3D stacked transistor (CFET) technology with self-aligned direct back contact and back gate contact (code T1-2). This technology combines CFET (3D stacked transistors) with self-aligned direct back contact and back gate contact (code T1-2).

IBM Research's 2nm nanosheet FET back power supply technology (also selected for the joint research team including TSMC (code TSF2-3)) and TSMC's miniaturization technology for two-dimensional transition metal dichalcogenide (MoS2) channel transistors (code T1-4) have been selected.

Word line air gap isolation supports the expansion of 3D NAND flash memory.

Next, in "next-generation storage technology," Micron Technology's 3D NAND flash memory cell thinning technology (code T1-3) and Micron's fine transistor technology for ferroelectric non-volatile DRAM (code T17-2), SK Hynix's Selector-Only Memory (SOM) technology (code T1-5), and the ferroelectric non-volatile SRAM technology of the joint research group including Sony Semiconductor Solutions (code T2-1) have been selected as notable papers.Micron Technology has developed a 3D NAND flash memory cell thinning technology (code T1-3). Air gaps are introduced in the inter-layer insulating film between the stacked word lines to reduce the parasitic capacitance of the word lines, and the charge trapping area is separated for each cell to suppress interference between adjacent cells.

Micron Technology has developed a microcrystalline transistor technology for ferroelectric non-volatile DRAM (code T17-2). By using dual-gate thin-film transistor technology, a small cell selection transistor with a size of 4F^2 (F^2 is the square of the design rule) has been realized.

SK Hynix has developed a Selective Only Memory (SOM) technology (code T1-5). A prototype has been made with a cross-point structure of a half-pitch of 16 nm, which is sufficient for SOM.

A joint research team including Sony Semiconductor Solutions has developed a ferroelectric non-volatile SRAM technology, which has made a 16Kbit non-volatile SRAM macro prototype using a 1T1C cell system with a cell selection transistor and an HZO-based ferroelectric capacitor. A 100% manufacturing yield has been achieved using 130nm technology.

Incorporating the effects of temperature changes into the performance evaluation of 1nm and 0.5nm generation logic

In the "All-oxide material transistor technology" category, the three-dimensional vertical integration technology of indium oxide (In2O3) material by the joint research team of Purdue University and Samsung (code T4-1) was selected as a noteworthy paper. The vertical transistor is composed of a thin-film channel made of indium oxide and a thick-film gate electrode. The thin film is formed using atomic layer deposition (ALD) technology.

In "Performance evaluation of Angstrom generation PPA performance considering thermal effects," a special paper (code T5-4) was selected. We evaluated the PPA of the 10A generation (1nm generation) nanosheet FET and the 5A generation (0.5nm generation) monolithic complementary FET (CFET).

Belgian imec first demonstrated a functional monolithic CFET device.The Belgian microelectronics research center imec has for the first time demonstrated a CMOS CFET device with stacked bottom and top source/drain contacts. Although the results were obtained using front-side lithography for both contacts, imec also demonstrated the feasibility of transferring the bottom contacts to the backside of the wafer, which can increase the yield of the top devices from 11% to 79%.

According to imec, its logic technology roadmap envisions the introduction of complementary field-effect transistor (CFET) technology in the A7 node device architecture. If complemented by advanced wiring technology, CFET is expected to reduce the standard cell height from 5T to 4T or even lower without sacrificing performance. Among the different methods of integrating nMOS and pMOS vertical stack structures, monolithic integration is considered to be the least disruptive compared to the existing nanosheet process flow.

The functional monolithic CMOS CFET device with top and bottom contacts demonstrated for the first time by imec at the 2024 VLSI Symposium has a gate length of 18nm, a gate pitch of 60nm, and a vertical spacing of 50nm between n-type and p-type. The process flow proposed by imec includes two CFET-specific modules: middle dielectric isolation (MDI) and stacked bottom and top contacts.

The fastest chip set helps build the next generation of wireless systems.

According to researchers from the National Institute of Information and Communications Technology in Japan and the Tokyo Institute of Technology, a new D-band silicon complementary metal-oxide-semiconductor (CMOS) transceiver chip set with a 56GHz signal chain bandwidth has achieved the highest wireless transmission speed of 640Gbps.

To process the increasing data traffic at faster speeds, wireless systems need to operate at higher millimeter wave bands. The current high-frequency 5G system can provide speeds up to 10Gbps, operating in the 24-47GHz band. People have been exploring higher frequency bands, and it is crucial to study transmitters and receivers that can maintain signal strength and are cost-effective.

The D-band 114-170GHz CMOS transceiver chip set developed this time has a signal chain bandwidth of 56GHz, with the transmitter integrated circuit chip size of 1.87mm×3.30mm and the receiver integrated circuit chip size of 1.65mm×2.60mm.

In the capability assessment, the device achieved high linearity for multi-level modulation schemes such as 16QAM and 32QAM, solving the main obstacle of previous integrated circuit transceivers. In particular, the performance of the chip set in a multiple-input multiple-output configuration with 4 transmitters and 4 receivers is impressive: each antenna can handle its own data stream, enabling fast communication, with a speed of 160Gbps per channel when using 16QAM modulation. Overall, the total speed reaches 640Gbps.These transmission speeds represent a significant leap, being 10 to 100 times faster than current 5G systems. Researchers have stated that this is the highest wireless transmission rate achieved to date, realized using low-cost CMOS technology, making mass production cost-effective. This chipset is expected to become the next generation of wireless systems, supporting applications such as autonomous driving vehicles, telemedicine, and advanced virtual reality experiences.