Has the Era of Copper Come to an End?

With the continuous decline in the efficiency of copper interconnect technology, chip manufacturers are increasingly focusing on new interconnect technologies, laying the foundation for performance improvements and heat reduction in future nodes and advanced packaging, indicating a possible major shift.

The introduction of copper interconnect technology in 1997 disrupted the standard of tungsten vias/aluminum wire metallization schemes at the time. The dual-Damascene integration scheme replaced "dry" processes such as plasma etching and deposition with "wet" processes like electroplating and CMP. At that time, manufacturers were striving to minimize RC delay in the face of more complex interconnect structures.

Nearly thirty years later, the semiconductor industry has come to a similar crossroads. The scaling down of linewidths is approaching the mean free path of copper's electrons. Barrier layers are taking up an increasingly larger share of the total available linewidth. The demand for alternatives to copper is growing. However, like most radical changes, manufacturers want to delay this change as much as possible.

Results recently presented at the IEEE Interconnect Technology Conference show that there are still opportunities to optimize copper.

Making the Most of Copper

As interconnect dimensions shrink, the interface and its characteristics are more important to electrical performance than the material's own characteristics. Jongmin Baek, a senior engineer at Samsung Semiconductor, and his colleagues specifically studied how to optimize the barrier and etch stop layers required for copper to improve overall performance. For example, in the contact metal-spacer test medium, the team reduced the sidewall barrier layer thickness by one-third and increased contact resistance by 2% using sidewall plasma pre-treatment.Samsung researchers have paid special attention to the barrier layer at the bottom of through-vias. Since the metal through-vias are located on metal lines, this barrier layer does not need to serve as electrical insulation or diffusion blocking. It is merely a byproduct of sidewall deposition, but it can account for more than 60% of the via resistance. Selective deposition methods are commonly used to reduce deposition at the bottom of through-vias. In Baek's work, a polymer inhibitor improved selectivity compared to the self-assembled monolayers typically used, reducing resistance by 20%.

Modern interconnect schemes rely on various carbon-doped oxides to achieve the "C" part of circuit RC delay. Materials with lower density have a lower dielectric constant (k), making them more attractive. Additional work by Samsung's Kang Sub Yim considered the consumption of carbon on the dielectric surface by plasma etching. Etching damage to low-k dielectric materials increases the effective dielectric constant, thereby increasing the circuit's capacitance. Denser materials, typically with a k-value above 3.0, are more resistant to plasma etching damage and may provide a lower effective k-value in features smaller than 30nm. For features smaller than about 30nm, the impact of surface carbon consumption on capacitance is greater than that of the bulk dielectric constant.

Yim's team also used surface silanization to recover etching damage. However, Baek noted that surface treatment of dielectric sidewalls carries the risk of metal contamination exposed at the bottom of the via. Instead, Baek's team used a thermal recovery process with proprietary chemistry to restore surfaces terminated with Si-OH after etching to Si-CH3 termination.

The full encapsulation of copper wires includes a metal cap layer—typically cobalt—to reduce electromigration, followed by an insulating etch stop and barrier layer. Due to scaling, these layers are becoming a larger part of the bus thickness. To improve the interface with the cap layer, Baek added plasma pre-treatment before the etch stop layer deposition. As a result, they saw a 30% reduction in copper wire stress and a 10% reduction in via resistance. Yim achieved similar results independently.

Ruthenium vias, then lines

Despite all these developments being promising, a long-term alternative to copper is still needed. In particular, vias, due to their small size and large quantity, are dominating the overall interconnect resistance. In the first four or five interconnect layers, the metal wires are very short and do not contribute much to the resistance. Therefore, an alternative is to use a transitional hybrid metallization scheme that combines copper wires with materials such as tungsten, ruthenium, or molybdenum for vias.

IMEC simulations show that using ruthenium vias for the first four layers of interconnect stacks can reduce overall resistance by up to 60%. To integrate ruthenium vias with copper wires, they suggest depositing a TaN barrier layer only on the dielectric sidewalls, with ruthenium directly deposited on the exposed copper. Any such scheme requires good dielectric surface passivation and good ruthenium selectivity control. A preferred cluster tool process is used because removing the native oxide from the exposed copper may damage the dielectric passivation.

Because ruthenium can be deposited or etched in various ways and does not require a barrier layer, it opens the door to more flexible integration schemes. For example, IMEC R&D engineer Giulio Marti and his colleagues benchmarked three different fully self-aligned via processes. The first, and most traditional, uses EUV self-aligned double patterning, where the spacer lines created are used to define the metal lines (SADP-SIM). After transferring the spacer pattern to a SiN hard mask, selective RIE etching patterned the ruthenium metal layer, followed by SiO2 deposition. A highly selective etch aligned the via openings with the remaining SiN features, followed by CVD ruthenium deposition to fill them.

The other two options considered by Marti are based on pillar vias, with a second layer of ruthenium deposited above the first, separated by an etch stop layer. In these schemes, pattern transfer uses a two-step ruthenium etch. First, a high-aspect-ratio etch cuts the required metal lines in both layers. Then, a spin-on dielectric material fills these trenches, with a hard mask on top. An inverse-tone EUV patterning hard mask protects the desired via pillars, while the previous etch stop layer protects the metal lines below. Marti found that the two pillar via options increased process steps but increased the process window. In particular, this approach prevents bridging between vias and adjacent lines.An alternative approach, proposed by another R&D engineer at imec, Chen Wu and his colleagues, uses SADP (Self-Aligned Double Patterning) intervals to define dielectric features, rather than metal. In this SADP-SID (Self-Aligned Double Patterning-Spacer-Isolated Double Patterning) scheme, the hard mask material is deposited between the spacer pillars, which are then removed. Although this method increases process complexity, it means that the metal features are directly defined by the mask, providing designers with more flexibility and control over feature sizes.

However, regardless of the specific method used, Wu emphasizes that an optimized ruthenium etching and deposition process will be crucial. The tapered profile at the base of the ruthenium features, the foot, and the incomplete removal of the TiN adhesion layer may reduce the spacing between adjacent lines, leading to leakage.

Integrated scheme is just the beginning

A successful process integration scheme requires careful attention to all component layers. For ruthenium, the optimization process has only just begun. Jack Rogers and his colleagues at the Albany Technology Center of TEL (Tokyo Electron Limited) have studied the impact of adhesion layer process conditions on ruthenium deposition behavior. Ruthenium films on PVD (Physical Vapor Deposition) and ALD (Atomic Layer Deposition) TiN have different grain orientations, different grain orientation distributions, and different resistivities. Larger and more uniform Ru grains seem to reduce resistivity, at least when the grains are smaller than the overall interconnect size.

Although ruthenium interconnects will require fewer auxiliary layers than copper—which is partly the purpose— the reintroduction of metal etching and dielectric filling processes will certainly keep process engineers busy in the coming years.